High speed data weighted averaging (DWA) to binary converter circuit
US11563443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Jul 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.