Electrical power operating states for core logic in a memory physical layer
US11567557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2019 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device has a memory functional block that includes memory circuits and a memory physical layer (PHY) functional block with core logic that controls operations in the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device also includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller sets the switch so that electrical power is provided from the memory PHY voltage regulator to the core logic in a full power operating state. The controller sets the switch so that electrical power is provided from the system voltage regulator to the core logic in one or more low power operating states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.