Patent · US Active

Latch circuitry for memory applications

US11568926B2 · kind B2 · utility

1Cited by

5References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Andy Wangkun Chen · Austin, US
Teresa Louise McLaurin · Dripping Springs, US
Frank David Frederick · Austin, US
Richard Slobodnik · Austin, US
Yew Keong Chong · Austin, US

Key dates

Filing date	Nov 23, 2020
Grant date	Jan 31, 2023
Priority date	—
Expiry date	Jan 13, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.