Memory including a plurality of portions and used for reducing program disturbance and program method thereof
US11568941B2 · kind B2 · utility
0Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Sep 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x−2)th word line, a second voltage to an (x−1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.