TSV coupled integrated circuits and methods

US11569219B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Rahul Mathur · Austin, US
• Xiaoqing Xu · Austin, US
• Andy Wangkun Chen · Austin, US
• Mudit Bhargava · Austin, US
• Brian Tracy Cline · Austin, US
• Saurabh Sinha · Danbury, US

Key dates

• Filing date: Oct 22, 2020
• Grant date: Jan 31, 2023
• Expiry date: Oct 22, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06544
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.