DEPOP using cyclic selective spacer etch

US11569370B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Leonard P. GULER · Hillsboro, US
• Vivek Thirtha · Portland, US
• Shu Zhou · Portland, US
• Nitesh Kumar · Pune, IN
• Biswajeet Guha · Hillsboro, US
• William Hsu · Hillsboro, US
• Dax M. Crum · Beaverton, US
• Oleg Golonzka · Beaverton, US
• Tahir Ghani · Portland, US
• Christopher KENYON · Portland, US

Key dates

• Filing date: Jun 27, 2019
• Grant date: Jan 31, 2023
• Expiry date: May 30, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.