Method and apparatus for executing vector instructions with merging behavior
US11573801B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Sep 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.