Patent · US Active

Logic built-in self-test of an electronic circuit

US11574695B1 · kind B1 · utility

0Cited by

7References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Alejandro Alberto Cook Lobo · Renningen, DE
Thomas Gentner · Eppelheim, DE
Michael Kugel · Eppelheim, DE
Otto A. Torreiter · Echterdingen, DE

Key dates

Filing date	Jul 29, 2021
Grant date	Feb 7, 2023
Priority date	—
Expiry date	Jul 29, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/32
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.