Semiconductor test system and method
US11574696B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Apr 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor test method. The semiconductor test method includes the operations of: receiving a source code written in an interpreted language; and performing, by a first test apparatus, a first test on a device under test (DUT) based on the source code. The operation of performing, by the first test apparatus, the first test on the DUT based on the source code includes the operations of: interpreting, by a processor, the source code to generate a first interpreted code; and performing the first test on the DUT according to the first interpreted code. The first test apparatus is configured to execute the first interpreted code written in a first language.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.