Methods for forming conductive vias, and associated devices and systems
US11574842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | May 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/535
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.