Bypassed gate transistors having improved stability
US11575037B2 · kind B2 · utility
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20References
29Claims
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Key dates
| Filing date | Jun 22, 2020 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Jul 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.