Patent · US Active

Instruction address translation and caching for primary and alternate branch prediction paths

US11579884B2 · kind B2 · utility

6Cited by

7References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Ashok Tirupathy Venkatachar · Santa Clara, US
Steven R. Havlir · Austin, US
Robert B. Cohen · Austin, US

Key dates

Filing date	Jun 26, 2020
Grant date	Feb 14, 2023
Priority date	—
Expiry date	Jun 26, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/1027
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Techniques for performing instruction fetch operations are provided. The techniques include determining instruction addresses for a primary branch prediction path; requesting that a level 0 translation lookaside buffer (“TLB”) caches address translations for the primary branch prediction path; determining either or both of alternate control flow path instruction addresses and lookahead control flow path instruction addresses; and requesting that either the level 0 TLB or an alternative level TLB caches address translations for either or both of the alternate control flow path instruction addresses and the lookahead control flow path instruction addresses.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.