Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column
US11581037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Aug 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.