Semiconductor package, and package on package having the same
US11581263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2020 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Nov 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.