Patent · US Active

Three-dimensional memory devices having through array contacts and methods for forming the same

US11581322B2 · kind B2 · utility

0Cited by
2References
20Claims
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Inventors

Key dates

Filing dateNov 21, 2020
Grant dateFeb 14, 2023
Priority date—
Expiry dateFeb 6, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/50
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.