Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer

US11581406B2 · kind B2 · utility

Assignee

• Daedalus Prime LLC · US

Inventors

• Stephen M. Cea · Hillsboro, US
• Roza Kotlyar · Portland, US
• Harold W. Kennel · Portland, US
• Anand S. Murthy · Beaverton, US
• Glenn A. Glass · Portland, US
• Kelin J. Kuhn · Beaverton, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Nov 1, 2021
• Grant date: Feb 14, 2023
• Expiry date: Nov 1, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/405

Abstract

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.