Thread-based processor halting
US11586443B2 · kind B2 · utility
3Cited by
9References
30Claims
0Family size
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Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jan 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for thread-based processor halting are described herein. A processor monitors control-status register (CSR) values that correspond to a halt condition for a thread. The processor then compares the halt condition to a current state of the thread and halts in response to the current state of the thread meeting the halt condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.