System and method for scalable hardware-coherent memory nodes

US11586541B2 · kind B2 · utility

Assignee

• Hewlett Packard Enterprise Development LP · US

Inventors

• Derek Schumacher · Auburn, US
• Randy Passint · Chippewa Falls, US
• Thomas Edward McGee · Chippewa Falls, US
• Michael Malewicki · Chippewa Falls, US
• Michael S. Woodacre · Winchester, GB

Key dates

• Filing date: Jul 31, 2020
• Grant date: Feb 21, 2023
• Expiry date: Jul 31, 2040

Classification

• Technology area (CPC —): General

Abstract

One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.