Secured memory
US11586778B2 · kind B2 · utility
2Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2018 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Sep 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.