Binary metal liner layers
US11587873B2 · kind B2 · utility
0Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jun 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76864
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.