Field effect transistor including gate insulating layer formed of two-dimensional material
US11588034B2 · kind B2 · utility
3Cited by
3References
26Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 1, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Oct 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.