Circuit structure with gate configuration
US11588038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | May 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.