Combining load or store instructions

US11593117B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Harsh Thakker · Austin, US
• Thomas Philip Speier · Holly Springs, US
• Rodney Wayne Smith · Raleigh, US
• Kevin JAGET · Raleigh, US
• James Norris Dieffenderfer · Apex, US
• Michael William Morrow · Cary, US
• Pritha Ghoshal · Raleigh, US
• Yusuf Cagatay Tekmen · Raleigh, US
• Brian Michael Stempel · Raleigh, US
• Sang Hoon Lee · Austin, US
• Manish Garg · Cary, US

Key dates

• Filing date: Jun 29, 2018
• Grant date: Feb 28, 2023
• Expiry date: Oct 13, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3832
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.