Memory including a plurality of portions and used for reducing program disturbance and program method thereof
US11594288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Oct 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.