Method for reducing oscillation during turn on of a power transistor by regulating the gate switching speed control of its complementary power transistor

US11595035B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Zheming Li · Bayreuth, DE
• Mark-Matthias Bakran · Erlangen, DE
• Daniel Domes · Schwäbisch Hall, DE
• Robert Maier · Babenhausen, DE
• Franz-Josef Niedernostheide · Hagen am Teutoburger Wald, DE

Key dates

• Filing date: Aug 27, 2021
• Grant date: Feb 28, 2023
• Expiry date: Aug 27, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K17/284
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.