Patent · US Active

Nanoscale-aligned three-dimensional stacked integrated circuit

US11600525B2 · kind B2 · utility

0Cited by

3References

29Claims

0Family size

Assignee

The Board of Regents of the University of Texas System · US

Inventors

Sidlgata V. Sreenivasan · Austin, US
Paras Ajay · Austin, US
Aseem Sayal · Austin, US
Ovadia Abed · Austin, US
Mark W. McDermott · Austin, US
Jaydeep P. Kulkarni · Portland, US
Shrawan Singhal · Austin, US

Key dates

Filing date	Dec 21, 2018
Grant date	Mar 7, 2023
Priority date	—
Expiry date	Mar 14, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1437
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.