Plurality of transistor packages with exposed source and drain contacts mounted on a carrier

US11600558B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Tomasz Naeve · Finkenstein, AT
• Ralf Otremba · Kaufbeuren, DE
• Thorsten Scharf · Regensburg, DE
• Markus Dinkel · Unterhaching, DE
• Martin Gruber · Schwandorf, DE
• Elvir Kahrimanovic · Villach, AT

Key dates

• Filing date: Apr 10, 2020
• Grant date: Mar 7, 2023
• Expiry date: Mar 11, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H02P2201/03
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.