Testing device and method for integrated circuit package
US11604211B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Aug 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/045
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing device for testing an integrated circuit package is provided, including a printed circuit board having a first surface, a second surface, and multiple conductive layers between the first and second surfaces. A metal layer is formed on the second surface and is electrically connected to one of the conductive layers that is grounded. A testing socket is disposed over the first surface. A conductive fastener secures the testing socket to the printed circuit board and is electrically connected to the metal layer. A cover is disposed over the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket. The cover has a conductive surface in contact with the integrated circuit package. A conductive element assembly is disposed between the cover and the testing socket and is electrically connected to the conductive surface and the conductive fastener.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.