In-memory full adder
US11604850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2020 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Jun 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit. The full adder unit does not overwrite any of the bits when a full adder table indicates that the sum bit and the carry out bit are equivalent to the second bit and the carry-in bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.