Memory programming with selectively skipped verify pulses for performance improvement
US11605437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Sep 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at least one data state, the later programming pass includes maintaining a count of the programming loops of the later programming pass. The later programming pass also includes inhibiting or slowing programming of the memory cells being programmed to one of the data states during a predetermined program count verify (PCV) programming loop and a PCV−1 programming loop and skipping a verify operation for all programming loops prior to a PCV+1 programming loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.