Methods of forming doped silicide power devices
US11605741B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 23, 2020 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | May 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67754
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.