Semiconductor device with stacked chips and method for fabricating the same
US11610878B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Nov 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method includes providing a bottom substrate; bonding a first stacking chip and a second stacking chip onto the bottom substrate; conformally forming a first isolation layer to cover the first and second stacking chips and to at least partially fill a gap between the first and second stacking chips; performing a thinning process to expose back surfaces of the first and second stacking chips; performing a removal process to expose through substrate vias of the first and second stacking chips; forming a first capping layer to cover the through substrate vias of the first and second stacking chips; and performing a planarization process to expose the through substrate vias of the first and second stacking chips and provide a substantially flat surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.