Void elimination for gap-filling in high-aspect ratio trenches
US11610982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | May 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.