Method for writing in a non-volatile memory according to the ageing of the memory cells and corresponding integrated circuit
US11615857B2 · kind B2 · utility
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27Claims
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Key dates
| Filing date | Apr 6, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Apr 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.