3-D NAND control gate enhancement
US11622489B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Sep 16, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Sep 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.