Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers
US11625283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2021 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Nov 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/4557
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.