Arnav GOEL
19Patents
4h-index
36Co-inventors
52Inventor score
Filing activity: Feb 28, 2019 → Jun 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11182221B1 | Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS) | Physics | 16 | Active |
| US11182264B1 | Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS) | Physics | 11 | Active |
| US11625284B2 | Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers | Physics | 5 | Active |
| US11625283B2 | Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers | Physics | 4 | Active |
| US11886930B2 | Runtime execution of functions across reconfigurable processor | Physics | 4 | Active |
| US11609798B2 | Runtime execution of configuration files on reconfigurable processors with varying configuration granularity | Physics | 4 | Active |
| US11886931B2 | Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers | Physics | 3 | Active |
| US12210468B2 | Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation | Physics | 1 | Active |
| US11809908B2 | Runtime virtualization of reconfigurable data flow resources | Physics | 1 | Active |
| US12380041B2 | Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations | Physics | 0 | Active |
| US11983141B2 | System for executing an application on heterogeneous reconfigurable processors | Physics | 0 | Active |
| US12346729B2 | Runtime virtualization of reconfigurable data flow resources | Physics | 0 | Active |
| US12298932B2 | Load balancing system for the execution of applications on reconfigurable processors | Physics | 0 | Active |
| US12169459B2 | Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation | Physics | 0 | Active |
| US12229057B2 | Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors | Physics | 0 | Active |
| US11936559B2 | Fast receive re-convergence of multi-pod multi-destination traffic in response to local disruptions | Electricity | 0 | Active |
| US12242403B2 | Direct access to reconfigurable processor memory | Physics | 0 | Active |
| US11782760B2 | Time-multiplexed use of reconfigurable hardware | Physics | 0 | Active |
| US10965589B2 | Fast receive re-convergence of multi-pod multi-destination traffic in response to local disruptions | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.