DRAM with selective epitaxial cell transistor
US11626407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2022 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Mar 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.