Patent · US Active

Flexible sizing and routing architecture

US11631439B1 · kind B1 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Sriram Thyagarajan · Austin, US
Yew Keong Chong · Austin, US
Munish Kumar · Sindhar, IN
Andy Wangkun Chen · Austin, US
Rajiv Kumar Sisodia · Bengaluru, IN

Key dates

Filing date	Oct 29, 2021
Grant date	Apr 18, 2023
Priority date	—
Expiry date	Oct 29, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.