Method for manufacturing semiconductor structure
US11631656B2 · kind B2 · utility
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2References
9Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 7, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Dec 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a first die, a second die, and a first conductive via. The first die includes a first dielectric layer and a first landing pad embedded in the first dielectric layer. The second die includes a second dielectric layer and a second landing pad embedded in the second dielectric layer. The first die is disposed on the second die. The second landing pad has a through-hole. The first conductive via extends from the first landing pad toward the second landing pad and penetrates through the through-hole of the second landing pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.