Non-volatile memory structure using semiconductor layer as floating gate and bulk semiconductor substrate as channel region

US11631772B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Thomas Melde · Dresden, DE
• Stefan Dünkel · Dresden, DE
• Ralf Richter · Dresden, DE

Key dates

• Filing date: Jan 13, 2021
• Grant date: Apr 18, 2023
• Expiry date: Jan 13, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00

Abstract

A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.