Method of forming memory cell
US11632889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Aug 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.