Clustered parity for NAND data placement schema
US11635894B2 · kind B2 · utility
4Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2019 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Jun 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.