Manufacturing method of chip package structure
US11637047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2022 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.