Method for preparing semiconductor memory device with air gaps for reducing capacitive coupling
US11638375B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Dec 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.