Procedures for improving efficiency of an interconnect fabric on a system on chip
US11640362B2 · kind B2 · utility
1Cited by
29References
20Claims
0Family size
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Key dates
| Filing date | Apr 12, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Apr 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/7453
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.