Device and method for accelerating matrix multiply operations
US11640444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Jul 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.