Selective accelerated sampling of failure- sensitive memory pages
US11644979B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Apr 7, 2022 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Apr 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.