Electrical isolation structure using reverse dopant implantation from source/drain region in semiconductor fin

US11646361B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Arkadiusz Malinowski · Malta, US
• Alexander M. Derrickson · Troy, US
• Haiting Wang · Clifton Park, US

Key dates

• Filing date: Mar 4, 2021
• Grant date: May 9, 2023
• Expiry date: Jul 23, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.