Sense amplifier mapping and control scheme for non-volatile memory
US11651800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.